Project Description

This project is a port of Grant Searles Cyclone II multicomputer project to the S100 Cyclone 4 FPGA Z80 board developed by John Monahan. After building Johns card, I got interested in implementing an MMU in the FPGA so I could use banked ram in CPM3 to access all of the 512K ram on Johns card. I found Grants project that had a very nice MMU implentation written in VHDL. Grant had used a Cyclone II FPGA card to implement a very extensive and well designed framework for emulating various CPU's, I/O devices and operating systems. I considered a couple of options to explore... port the MMU to Johns code and build a banked memory version of CPM3, or port Grants code and ideas to Johns board and try running the images and OS options that were available with Grants design. As it turned out, I learned a great deal porting Grants design to the FPGA_Z80 hardware. This is still a work in progress, but I am at a point, that I wanted to share my developments with other builders of Johns card. So far, I have implemented

• the SPI interface to the first uSD card - the hard drive emulation
• a port to read from the DIP switches
• a port to write to the 8 LED bank on the top of Johns card
• a serial UART with fifo buffer for the console
• a single bit port for driving the buzzer
• MMU using 32 16k pages that get mapped into 1 of 4 16K slots in the Z80 address space
• A memory test that tests all of the 512K ram chip using rolling page setups.

• spi interface to the RTC hardware ( done )
• some minimal S100 bus functionality like read/write off board IO ports
• VGA display possibly with its own Z80 to get the video buffer out of the system Z80 memory space.
• VGA attributes.. flashing, inverse video, underline/block cursor, character color
• maybe a tek 4010/4014/4016 graphics terminal emulation
• PS/2 keyboard support
• implement printer port ( now using this port for a second serial port )
• find I/O for the second serial port (currently stubbed with no assigned I/O) (done)
• experiment with higher speed clocks
• change the disk format from 512 directory entries to 1024 entries. Impacts a lot of code in every operating system
• In the Quartus project, I would like to understand how to generate Microcomputer.sdc to eliminate all the timing constraint warnings.

Updates

Booting CPM3

System Requirements

• a functioning FPGA_Z80 card from the S100Computers site.
• Intel Quartus Prime 21.1 Lite Edition installed on your PC (I use linux)
• a USB Blaster for programming the FPGA card
• the project files included below for the FPGA design
• the micro SD card image included below contaning 18 8MB disk images

# disk format for grant searles images
diskdef gsearle
  seclen 512
  tracks 512
  sectrk 32
  blocksize 4096
  maxdir 512
  skew 0
  boottrk 1
  os 3
end

Source Code